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PLC Performance Enhancement by Field Programmable Gate Array Design

The post PLC Performance Enhancement by Field Programmable Gate Array Design first appeared on the ISA Interchange blog site.

This post is an excerpt from the journal ISA Transactions.  All ISA Transactions articles are free to ISA members, or can be purchased from Elsevier Press.

Abstract: PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed andPLC-performance-enhancement poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx’s Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and  applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.

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2006 Elsevier Science Ltd. All rights reserved.

Source: ISA News